Integrated circuit (IC) devices can include a number of sections formed in one or more substrates that are electrically interconnected to one another. In order to provide increased operating speeds, it is desirable to provide as fast a signal transmission speed as possible for signal paths that interconnect different sections. For some integrated circuit devices, critical timing paths can be identified prior to the fabrication of the device, and thus optimized (e.g., utilize large signal driving devices, minimize routing lengths, increase signal line cross sectional size to reduce resistance).
However, for other integrated circuit devices signal paths can be configured after the device has been manufactured, by connecting different signal paths with switches. In such cases, complete signal routing paths are unknown at the time of fabrication and thus cannot be optimized in the manner described above. Further, because configuration of signal paths can depend upon a series of switches, signal switch construction can limit overall performance of the devices. For example, programmable logic devices (PLDS) can often include signal paths configurable by enabling (placing into a relatively low impedance state) or disabling (placing into a relatively high impedance state) various switching devices. Programmable logic devices can include, as but a few examples, complex PLDs (CPLDs) and programmable gate arrays (PGAs) including field PGAs (FPGAs).
Thus, it can be desirable to reduce both resistance and capacitance along programmable switching paths to as great an extent as is possible.
Another issue that can be presented by PLD devices is that of bus contention. A typical PLD can include a number of volatile storage circuits that store configuration data for enabling logic functions and/or switch paths within the PLD. However, when power is initially applied to the device, or the device is reset, such storage circuits can initially assume essentially random states. This can potentially lead to different blocks of a PLD driving a same bus line to different potentials.
To better understand various features of the disclosed embodiments, a conventional switching arrangement for an FPGA will now be described.
Referring now to FIG. 21, a portion of a conventional FPGA is shown a block diagram and designated by the general reference character 2100. Conventional FPGA 2100 can include a logic block 2102, connection blocks 2104-0 and 2104-1, and a switch block 2106. Logic block 2102 can provide a logic function determined according to stored configuration data.
Connection blocks (2104-0 and 2104-1) can selectively connect inputs of logic block 2102 or outputs from logic block 2102 to routing signal lines. In the particular example of FIG. 21, connection block 2104-0 can provide programmable connections between a horizontal routing path 2108 and logic block 2102. Connection block 2104-1 can provide programmable connections between vertical routing path 2110 and logic block 2102.
Switch block 2106 can provide programmable connections for horizontal routing path 2108, for vertical routing path 2110, and for connecting signal lines of such paths to one another.
When power is initially applied to conventional FPGA 2100, the configuration data establishing the operation of logic block 2102 and/or the configuration data controlling the connection blocks (2104-0 and 2104-1) can be indeterminate. As a result, different logic blocks (e.g., 2102) can drive same lines along a routing path (2108 and 2110) to different levels. Such a result can draw undesirable large amounts of current, prevent or delay a subsequent configuration data writing operation, or even cause the FPGA 2100 to fail.
One conventional approach to addressing bus contention is to provide additional logic to control each switch within a connection block and/or switch block. Such logic ensures switches within such blocks are turned off until the FPGA 2100 device has been powered up and is stable. A drawback to such an approach can be the increase in switch size. In particular, if a switch is composed of a single metal-oxide-semiconductor (MOS) type switch transistor, utilizing a two-input complementary MOS (CMOS) NAND (or NOR) gate to control the switch can require an additional four transistors per switch, greatly increasing the overall area for the FPGA, as such devices can include many thousands or millions of such switches.
Yet another issue presented by PLD devices can be configuration data writing operations. In an FPGA, for example, configuration data can be shifted into a device in a serial fashion to configuration storage locations or write registers. In the latter case, such write registers can then be utilized to write data into configuration storage locations. In order to provide efficient use of FPGA resources, signal routing lines can serve dual purposes. In a programming operation, selected of such lines can be used to carry configuration data to configuration storage locations or write registers. However, once the device is programmed, such signal lines can be configured to route signals between logic blocks according to configuration data.
In order to provide such dual use functions, switch blocks (e.g., 2106 of FIG. 21) can include logic between configuration data stores and switches that can force switches into a particular state in order to route configuration data along a particular path. This can also consume valuable area in an FPGA device.